# -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition # Date created = 21:16:13 September 09, 2014 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # ZMachine_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone II" set_global_assignment -name DEVICE EP2C5T144C8 set_global_assignment -name TOP_LEVEL_ENTITY ZMachine set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:16:13 SEPTEMBER 09, 2014" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation set_global_assignment -name VERILOG_FILE ZMachine.v set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name BDF_FILE ZMachine.bdf set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_location_assignment PIN_142 -to address[16] set_location_assignment PIN_141 -to address[15] set_location_assignment PIN_48 -to address[14] set_location_assignment PIN_53 -to address[13] set_location_assignment PIN_139 -to address[12] set_location_assignment PIN_58 -to address[11] set_location_assignment PIN_60 -to address[10] set_location_assignment PIN_57 -to address[9] set_location_assignment PIN_55 -to address[8] set_location_assignment PIN_137 -to address[7] set_location_assignment PIN_136 -to address[6] set_location_assignment PIN_135 -to address[5] set_location_assignment PIN_134 -to address[4] set_location_assignment PIN_133 -to address[3] set_location_assignment PIN_132 -to address[2] set_location_assignment PIN_129 -to address[1] set_location_assignment PIN_126 -to address[0] set_location_assignment PIN_64 -to data[7] set_location_assignment PIN_65 -to data[6] set_location_assignment PIN_67 -to data[5] set_location_assignment PIN_69 -to data[4] set_location_assignment PIN_70 -to data[3] set_location_assignment PIN_121 -to data[2] set_location_assignment PIN_122 -to data[1] set_location_assignment PIN_125 -to data[0] set_location_assignment PIN_17 -to osc_clk set_location_assignment PIN_52 -to WE set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_location_assignment PIN_43 -to PE set_location_assignment PIN_63 -to ramCS set_location_assignment PIN_120 -to romCS set_global_assignment -name SDC_FILE zmachine.sdc set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE AREA set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ALWAYS set_location_assignment PIN_3 -to led0 set_location_assignment PIN_7 -to led1 set_location_assignment PIN_9 -to led2 set_location_assignment PIN_143 -to A18 set_location_assignment PIN_118 -to A17 set_location_assignment PIN_119 -to romOE set_location_assignment PIN_51 -to ramCE2 set_location_assignment PIN_59 -to ramOE set_location_assignment PIN_41 -to lcdCS set_location_assignment PIN_40 -to lcdReset set_location_assignment PIN_42 -to lcdRS set_location_assignment PIN_44 -to lcdRD set_location_assignment PIN_45 -to nadcCS set_location_assignment PIN_47 -to adcDout set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to adcDout set_global_assignment -name QIP_FILE altpll0.qip set_location_assignment PIN_144 -to reset set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to reset set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top